1. Technical Field
Embodiments of the present invention relate generally to data communication techniques. More particularly, embodiments relate to techniques for clocking data exchanges on a bidirectional data link between two interfaces.
2. Background Art
FIG. 1 illustrates a system 100 according to existing techniques for bidirectional package-to-package data communications between a processing device 102 and a memory device—e.g. a random access memory (RAM) 152. A processing interface 104 of processing device 102 coordinates a buffering of data for exchanging to/from processing unit 102—e.g. via a receive first-in-first-out (FIFO) buffer Rx FIFO 120 and/or a transmit buffer Tx FIFO 110. Processing interface 104 may, for example, include an analog front end of processing device 102. A RAM interface 150 coordinates data exchanges on behalf of RAM 152.
Processing interface 104 for processing unit 102 may include a transmit latch 114 in a transmit path 112 to carry data from Tx FIFO 110 to a bidirectional link DQ 140, while RAM interface 150 for RAM 152 may include a receive latch 164 in a receive path 162 to carry data from DQ 140 to RAM 152. A writing of data to RAM 152 by processing unit 102 may include clocked latching by transmit latch 114 and receive latch 164. In a corresponding manner, RAM interface 150 includes a transmit latch 174 in a transmit path 172 to carry data from RAM 152 to DQ 140, while processing interface 104 includes a receive latch 124 in a receive path 122 to carry data from DQ 140 to Rx FIFO 120. A reading of data in RAM 152 by processing unit 102 includes clocked latching by transmit latch 174 and receive latch 124.
To clock the latching of data to/from DQ 140, a clock source 130 circuit of processing interface 104 generates a clock signal CLKW 142—e.g. based on a received reference clock signal CLKRef 135. In addition to driving clocked latching of transmit latch 114 and receive latch 124, CLKW 142 is also provided to RAM interface 150 for clocked latching of data in receive latch 164 to RAM 152 and/or for clocked latching of data in transmit latch 174 to DQ 140. In receiving CLKW 142 from processing interface 104, RAM interface 150 needs to include signal recovery circuitry—e.g. a clean-up circuit 180—to filter noise components from CLKW 142 which are introduced by being generated at and/or transmitted from processing interface 104.
For clocking synchronization, existing clocking designs physically locate as clock source 130 in a central position of processing device 102 in order to provide shorter clock/phase distribution through a clock tree of the processor. Consequently, existing data processing techniques rely upon the ‘processor side’ of system 100 to provide to the ‘memory side’ a clock signal from the processor side clock source for coordinating the memory side latching of data to and/or from DQ 140. This reliance on a processor interface to provide a clock signal to a memory device interface comes at a premium at least insofar as it consumes valuable substrate surface area on the processor side.